View L9733XP_9101916.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

september 2013 doc id 11319 rev 11 1/34 1 l9733 octal self configuring low/high side driver features eight independently self configuring low/high drivers supply voltage from 4.5 v to 5.5 v r on(max) = 0.7 ? @ t j = 25 c, r on(max) = 1.2 ? @t j = 125 c minimum current limit of each output 1 a output voltage clamping min. 40 v in low-side configuration output voltage clamping max. -14 v in high-side configuration spi interface for outputs control and for diagnosis data communication additional pwm inputs for 3 outputs independent thermal shutdown for all outputs open load, short to gnd, short to vb, overcurrent diagnostics in latched or unlatched mode for each channel internal charge pump without need of external capacitor controlled sr for reduced emc description the l9733 is a highly flexible monolithic, medium current, output driver that incorporates 8 outputs that can be used as either internal low or high-side drives in any combination. outputs 1-8 are self-configuring as high or low- side drives. self-configuration allows a user to connect a high or low-side load to any of these outputs and the l9733 will dr ive them correctly as well as provide proper fault mode operation with no other needed inputs. in addition, outputs 6, 7 and 8 can be pwm controlled via a external pins (in6-8). this device is capable of switching variable load currents over the ambient range of -40 c to +125 c. the outputs are mosfet drivers to minimize vdd current requirements. for low-side configured outputs an internal zener clamp from the drain to gate with a breakdown of 50 v minimum will provide fast turn off of inductive loads. when a high-side configured output is commanded off after having been commanded on, the source voltage will go to (vgnd - 15 v). an 16 bit spi input is used to command the 8 output drivers either "on" or "off", reducing the i/o port requirement of the microcontroller. multiple l9733 can be daisy-chained. in addition the spi output indicates latched fault conditions that may have occurred. powersso-28 table 1. device summary order code package packing L9733XP powersso-28 (exposed pad) tube L9733XPtr powersso-28 (exposed pad) tape and reel l9733cn powersso-28 (exposed pad) tube l9733cntr powersso-28 (exposed pad) tape and reel www.st.com
contents l9733 2/34 doc id 11319 rev 11 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 functional operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 jump start conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 operation at low battery condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 operation at load dump condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.5 loss of protection against short to battery . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 electrical performance c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 spi characteristics and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 configurations for outputs 1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.1 low-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 high-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 outputs 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 outputs 6-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 drn1-8 susceptibility to negative voltage transients . . . . . . . . . . . . . . . . . 19 4.5 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.1 main power input (vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2 battery supply (vbat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.3 discrete inputs voltage supply (vdo) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 discrete inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.1 output 6-8 enable input (in6, ln7, ln8) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.2 reset input (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l9733 contents doc id 11319 rev 11 3/34 5.1 serial data output (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 serial data input (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 chip select (cs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 serial clock (sclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 initial input command register and fault register spi cycle . . . . . . . . . . . . 22 5.6 input command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 other l9733 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 charge pump usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 waveshaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 por register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 fault operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 low-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.1 no latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1.2 latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 high-side configured output fault operation . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.1 no latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2.2 latch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
list of tables l9733 4/34 doc id 11319 rev 11 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. spi characteristics and timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. bit command register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. command register logic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. fault register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. fault logic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
l9733 list of figures doc id 11319 rev 11 5/34 list of figures figure 1. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figure 3. do loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. output loading for slew rate measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5. spi input/output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. l9733 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8. l9733 hvac applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. l9733 powertrain applicative examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. optimized circuit layout to achieve proper emi/esd capability . . . . . . . . . . . . . . . . . . . . . 31 figure 11. powersso28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 32
pin description l9733 6/34 doc id 11319 rev 11 1 pin description figure 1. pin connection (top view) table 2. pin description n pin function 1 vdd 5 volt supply input 2 sclk spi serial clock input 3 cs spi chip select (active low) 4 src1 source pin of configurable driver #1 (0.7 ? rds on @ +25 c) 5 drn1 drain pin of configurable driver #1(0.7 ? rds on @ +25 c) 6 drn2 drain pin of configurable driver #2 (0.7 ? rds on @ +25 c) 7 src2 source pin of configurable driver #2 (0.7 ? rds on @ +25 c) 8 src3 source pin of configurable driver #3 (0.7 ? rds on @ +25 c) 9 drn3 drain pin of configurable driver #3 (0.7 ? rds on @ +25 c) 10 drn4 drain pin of configurable driver #4 (0.7 ? rds on @ +25 c) 11 src4 source pin of configurable driver #4 (0.7 ? rds on @ +25 c) 12 in6 discrete input used to pwm output driver #6 13 in7 discrete input used to pwm output driver #7 14 vbat battery supply voltage 15 gnd analog ground 16 in8 discrete input used to pwm output driver #8 17 res reset input (active low) 18 src5 source pin of configurable driver #5 (0.7 ? rds on @ +25 c) vdd sclk cs src1 drn1 src2 drn2 src3 drn3 drn6 src6 src7 drn8 drn7 src8 d1 d0 vdo 1 3 2 4 5 6 7 8 9 26 25 24 23 22 20 21 19 27 10 28 drn4 drn5 d06at544 src4 in6 in7 in8 res src5 11 12 13 18 16 17 15 14 vbat gnd
l9733 pin description doc id 11319 rev 11 7/34 note: the exposed slug must be soldered on the pcb and connected to gnd. 19 drn5 drain pin of configurable driver #5 (0.7 ? rds on @ +25 c) 20 drn6 drain pin of configurable driver #6 (0.7 ? rds on @ +25 c) 21 src6 source pin of configurable driver #6 (0.7 ? rds on @ +25 c) 22 src7 source pin of configurable driver #7 (0.7 ? rds on @ +25 c) 23 drn7 drain pin of low-side driver #7 (0.7 ? rds on @ +25 c) 24 drn8 drain pin of low-side driver #8 (0.7 ? rds on @ +25 c) 25 src8 source pin of configurable driver #8 (0.7 ? rds on @ +25 c) 26 di spi data in 27 do spi data out 28 vdo microcontroller logic interface voltage table 2. pin description (continued) n pin function
operating conditions l9733 8/34 doc id 11319 rev 11 2 operating conditions 2.1 operating range this part may not operate if taken outside the operating range. once the condition is returned to within the specified maximum rati ng or the power is recycled, the part will recover with no damage or degradation. 2.1.1 functional operative range 4.5 v ? v bat ? 18 v (-40 c ? t j ? 150 c); all the electrical capabilitie s are guaranteed by charac terization as reported in section 3: electrical performance characteristics . 2.1.2 jump start conditions 18 v ? v bat ? 27 v (-40 c ? t j ? 150 c); operation at jump start condition for a maximum duration of 1 minute. all ouputs are switched according to the commands on the spi bus or the pwm inputs. the spi bus and the inputs are functional during the jump-start condition. the over-temperature shutdown and over current protection of the device is not guaranteed to stay functional for vbat between 18 v and 27 v. the reliability and the functionality of the l9 733xp are not compromi sed when the jump- start condition is not repeated for more than five times. table 3. operating range symbol parameter value unit v dd supply voltage 4.5 to 5.5 v v bat (operative range) battery supply voltage 4.5v to 18 v v bat @ jsc 18 to 27 v bat @ low battery 3.5 to 4.5 v bat @ load dump 27 to 40 t j thermal junction temperature range -40 to 150 c snubbing voltage of drn1-8 min 50 vdc i ox output current 1-8 max 800 ma eso maximum clamping energy at switch-off 20 mj
l9733 operating conditions doc id 11319 rev 11 9/34 2.1.3 operation at low battery condition 3.5 v ? v bat ? 4.5 v (-40 c ? t j ? 150 c); all outputs are able to keep the status in according to the commands on the spi bus or the pwm inputs. switching commands entered via the spi bus might not be executed by the l9733 at low-battery condition. the spi bus and the inputs are functional during the low- battery condition. 2.1.4 operation at load dump condition 27 v ? v bat ? 40 v (-40 c ? t j ? 150 c) there is not an internal circuit that switches off the drivers during load dump condition. the over-temperature shutdown and over current protection of the device is not guaranteed to stay functional during load dump condition. 2.1.5 loss of protection a gainst short to battery when the battery supply voltage, v bat (pin 14) is switched off during a short-to-battery condition at a output in high-side configuration, the protection circuits are no longer functional, and the l9733 may fail with eos. 2.2 absolute maximum ratings this part may be irreparably damaged if taken outside the specified absolute maximum ratings. operation outside the absolute maximum ratings may also cause a decrease in reliability. table 4. absolute maximum ratings symbol parameter value unit v dd supply voltage -0.3 to 7 v v bat supply voltage -0.3 to 40 v cs,di,do,sclk,en,in6,in7,in8,vdo -0.3 to 7.0 v srcx pin min. -24 vdc max. value of v srcx = minimum of {v bat +1v ||| v drnx +0,3 v ||| +40 v} drn1-8 (1) 1. for the drnx the max asb value is the max clamp voltage (see table 6 on page 13 - drnx clamp voltage). -0.3 to 60 vdc i ol current limit of output 1-8 (-40 c) 2.5 a i op over current protection at output 1-8 (-40 c) 3 a maximum clamping energy 20 mj esd human body model - all pins 2 (2) 2. device is only protected vs. gnd. kv human body model - driver outputs 4 (2) kv
operating conditions l9733 10/34 doc id 11319 rev 11 2.3 thermal data table 5. thermal data symbol parameter min typ max unit t amb operating ambient temperature -40 - 125 c t stg storage temperature -50 - 150 c t j maximum operating junction temperature - - 150 c r th thermal shutdown temperature 151 175 200 c r th-hys thermal shutdown temperature hysteresis 7 10 25 c r th j-amb thermal resistance junction-to-ambient (1) 1. with 2s2p pcb thermally enhanced. --24c/w r th j-case thermal resistance junction-to-case - - 3 c/w
l9733 electrical performance characteristics doc id 11319 rev 11 11/34 3 electrical performance characteristics these are the electrical capabilities this part was designed to meet. it is required that every part meet these characteristics. 3.1 dc characteristics t amb = -40 to 125 c, v dd = 4.5 to 5.5 vdc, v bat = 4.5 to 18 vdc (high-side configuration), unless otherwise specified. table 6. dc characteristics symbol parameter conditions min typ max units in6v ih in6 input voltage - - 0.7vdo v in6v il 0.3vdo - - v i in6il in6 input current in6 = 0 vdc - - |10| ? a i in6ih in6 = vdo 10 - 100 ? a in7v ih in7 input voltage - - 0.7vdo v in7v il 0.3vdo - - v i in7il in7 input current in7 = 0 vdc - - |10| ? a i in7ih in7 = vdo 10 - 100 ? a in8v ih in8 input voltage - - 0.7vdo v in8v il 0.3vdo - - v i in8il in8 input current in8 = 0 vdc - - |10| ? a i in8ih in8 = vdo 10 - 100 ? a cs ih cs input voltage - - 0.7vdo v cs il 0.3vdo - - v i csih cs input current cs = vdo - - |10| ? a i csil cs = 0 vdc 10 - 100 ? a sclk ih sclk input voltage - - 0.7vdo v sclk il 0.3vdo - - v i sclkih sclk input current sclk = vdo - - |10| ? a i sclkil sclk = 0 vdc 10 - 100 ? a di ih di input voltage - - 0.7vdo v di il 0.3vdo - - v i diih di input current di = vdo - - |10| ? a i diil di = 0 vdc 10 - 100 ? a do ol do output voltages i do = 2.5 ma - - 0.4 v do oh i do = -2.5 ma vdo-0.6 - - v
electrical performance characteristics l9733 12/34 doc id 11319 rev 11 i dozol do tri-state currents do = 0 vdc - - |10| ? a i dozoh do = vdo - - |10| ? a res ih res input voltage - - 0.7vdo v res il 0.3vdo - - v i resil res input current res = 0 vdc 10 - 100 ? a i resih res = vdo - - |10| ? a por th power on reset threshold @ -40 c 2.8 - 4.2 v @ 25 c 2.8 - 3.7 @ 125 c 2 - 3.4 i slp vbat sleep current vdd = src1-8 = 0vdc drn1-drn8=18vdc, vb. sum currents (t amb > 0 c) (t amb @ -40 c) -- 10 3 ? a ? a i vbat vbat current vdd = 5 v all outputs commanded on --15ma i vdd max. vdd current all outputs commanded on - - 8.5 ma i vdd min. vdd current all outputs commanded off 0.5 - ma i drn1lk - i drn8lk drn1 - drn8 leakage currents (low-side) vdd = 0 vdc: src1-8 = 0 vdc drn1- drn8 = 16 vdc drn1- drn8 = 40 vdc --5 10 ? a ? a i src1lk - i src8lk. src1 ? src8 leakage currents (high-side) vdd = 0 vdc: src1-8 = 0 vdc drn1- 8 = 16 v drn1- 8 = 40 vdc ---5 -10 ? a ? a i drn1-8sink drn1 ? drn8 sink current (low-side) src1-8 = gnd di = ac00h r load ?? 11 k ? r load ?? 200 k ? 10 120 -100 280 ? a ? a r drn1-8 open load detection resistance vbat>=9v 11 - 200 k ? i drn1-8source source current drn1-drn8 = gnd -10 - -100 ? a i src1-8sink src1 ? src8 sink/source current (high-side) drn1- 8 = vb, di = ac00h scr1- 8 = vb 10 - 100 ? a i src1-8source scr1- 8 = gnd -18 - -100 ? a v drn1-8open drn1 ? drn8 open load voltage (low-side) src1- 8 = gnd, di = ac00h drn1- drn8 = open vdd=4.9 to 5.1 vdc 2.7 - 3.1 v src1- 8 = gnd, di = ac00h drn1- drn8 = open vdd = 4.5 to 5.5 v 2.5 - 3.5 v table 6. dc characteristics (continued) symbol parameter conditions min typ max units
l9733 electrical performance characteristics doc id 11319 rev 11 13/34 v src1-8open src1 ? src8 open load voltage (high-side) drn1 - drn8 drn1-8 = vb, di = ac00h scr1-8 = open 2.0 - 2.8 v i drn1limit - i drn8limit drn1 - drn8 current limits (low-side) di = acffh, di = aaffh src1 ? src8 = 0 vdc drn1 - drn8 = 4.5 - 16 vdc (t amb > 0 c) (t amb @ -40 c) 1 1 - 2.2 2.5 a a i drn1ovc - i drn8ovc drn1 - drn8 overcurrent threshold (low-side) di = ac00h, di = aa00h src1 ? src8 = 0 vdc drn1 - drn8 = 4.5 - 16 vdc (t amb > 0 c) (t amb - 40 c) 1 1 - 2.7 3 a a i src1limit - i src8limit src1 ? src8 current limits (high-side) di = acffh, di = aaffh drn1 - drn8 = vb src1 ? src8 = gnd (t amb > 0 c) (t amb - 40 c) 1 1 - 2.2 2.5 a a i src1ovc - i src8ovc overcurrent threshold (high-side) drn1 - drn8 = vbat src1 ? src8 = gnd (t amb > 0 c) (t amb - 40 c) 1 1 - 2.7 3 a a drn1 cl+ - drn8 cl + drn1 - drn8 clamp voltages (low-side) di = ac00h src1-8 = gnd, i drn1-8 = 350 ma 50 - 60 v src1 cl+ - src8 cl + src1 ? src8 clamp voltages (high-side) di = ac00h drn1-8 = vbat, i src1-8 = -350 ma -24 - -14 v v drn1-8open - drn1- 8 vthgnd short to gnd threshold distance from open load voltage (low-side) src1 ? src8 = gnd: decrease drn1 - drn8 until faults are ?set? 0.3 - 0.7 v drn1- 8 vthvbat - v drn1-8open drn1 - drn8 short to vbat threshold distance from open load voltage (low-side) di = ac00h src1 ? src8 = gnd: increase drn1 - drn8 until faults are ?not set? 0.3 - 0.7 v v drn1-8open - src1- 8 vthgnd src1 - src8 short to gnd threshold distance from open load voltage (high-side) di = ac00h drn1 ? drn8 = vb: decrease src1 - src8 until faults are ?not set? 0.2 - 0.6 v src1- 8 vthvbat - v drn1-8open src1 ? src8 short to vbat threshold distance from open load voltage (high-side) di = ac00h drn1 ? drn8 = vbat: increase scr1 - scr8 until faults are ? set? 0.2 - 0.6 v table 6. dc characteristics (continued) symbol parameter conditions min typ max units
electrical performance characteristics l9733 14/34 doc id 11319 rev 11 3.2 ac characteristics t amb = -40 to 125 c, v dd = 4.5 to 5.5 vdc, v bat = 4.5 to 18 vdc, unless otherwise specified rdson drn1-8 (1) on resistance (drn to src1-8) @ +125 c @ i drn = 350 ma - - 1.2 ? @ +25 c @ idrn = 350 ma - - 0.7 ? @ -40 c @ i drn = 350 ma - 0.5 ? drn1-8 ther (2) thermal shutdown temperature di = acffh, i drn1-8 = 1 ma, src1 ? src8 = gnd, increase temperature until drn1 - drn8 > 2 vdc, verify do bits 0-15 are ?set? 151 - 200 c drn1-8 hyst (2) hysteresis drn1 - drn8 < 2 vdc 5 - 15 c 1. r dsondrn1-8 ? 1.2 ? ; at v bat between 3.5 v and 27 v and t between -40 c and 150 c 2. design information, not tested. table 6. dc characteristics (continued) symbol parameter conditions min typ max units table 7. ac characteristics symbol parameter conditions min typ max units t filtdrn1-8 drn1 - drn8 open load & short to gnd filter time (low-side) (latch mode) di = ac00h, di = a3ffh src1 ? src8 = gnd 300 - 900 ? s t filtsrc1-8 src1 - src8 open load & short to vbat filter time (high-side) (latch mode) di = ac00h, di = a3ffh drn1 ? drn8 = vb 300 - 900 ? s t deldrn1-8 drn1 - drn8 overcurrent switch off delay (low-side) di = acffh, di = aa00h src1 ? src8 = gnd 10 - 75 ? s t delsrc1-8 src1 - src8 overcurrent switch off delay (high-side) di = acffh, di = aa00h drn1 ? drn8 = vb 10 - 75 ? s t res restart time after overcurrent switch off time (int) di = acffh, di = aa00h 120 - 450 ms drn1-8 htol slew rate turn on outputs loaded as figure 4 see figure 2 see figure 2 0.65 - 1.95 v/ ? s drn1-8 ltoh turn off (low-side) 0.5 - 1.5 v/ ? s
l9733 electrical performance characteristics doc id 11319 rev 11 15/34 figure 2. output turn on/off delays and slew rates src1-8 htol slew rate turn on outputs loaded as figure 4 see figure 2 see figure 2 0.65 - 1.95 v/ ? s src1-8 ltoh turn off (high-side) 0.5 - 1.5 v/ ? s drn1-8 tondly delay time tu r n o n outputs loaded as figure 4 see figure 2 see figure 2 2 - 20 ? s drn1-8 toffdly turn off (low-side) 10 - 100 ? s src1-8 tondly delay time tu r n o n outputs loaded as figure 4 see figure 2 see figure 2 2 - 20 ? s src1-8 toffdly turn off (high-side) 10 - 100 ? s drn1-8 offon delay delta drn1-8 toffdly - drn1-8 tondly 10 - 60 ? s src1-8 offon delay delta src1-8 toffdly - src1-8 tondly 10 - 60 ? s table 7. ac characteristics (continued) symbol parameter conditions min typ max units drn1-8tondly in 6-8 drn1-8 drn1-8 drn1-8toffdly drn1-8toffdly drn1-8ltoh drn1-8htol 90% 20% 20% 90% in1- 5 are available on wafer on ly src1-8tondly src1-8 src1-8 src1-8toffdly drn1-8ltoh drn1-8htol 90% 20% 20% 90% in1- 5 are available on wafer on ly src1-8tondly src1-8 src1-8 src1-8toffdly src1-8htol src1-8ltoh 80% 10% 10% 80% lsd hsd - in 6- 8 in 6- 8
electrical performance characteristics l9733 16/34 doc id 11319 rev 11 3.3 spi characteristics and timings t amb = -40 to 125 c, v dd = 4.5 to 5.5 vdc, v bat = 4.5 to 18 vdc, unless otherwise specified table 8. spi characteristics and timings symbol parameter conditions min typ max units dinc in input capacitance - - 20 pf sclk cin - - 20 pf do rise output data (do) rise time 50 pf from do to ground see figure 5 - - 70 ns do fall output data (do) fall time see figure 5 - - 70 ns do a access time see figure 6 --350ns do sum set up time see figure 6 20 - - ns do hm hold time see figure 6 10 - - ns do dis output data (do) disable time no capacitor on do, see figure 5 --400ns tth filt filter time all fault bits are ?set? 5 - 20 ? s sclkwid sclk width see figure 5 , @ f sclk = 5.4mhz (1) 185 - - ns sclklm sclk low time see figure 5 , @ f sclk = 5.4mhz (1) 58 - - ns sclkhm sclk high time see figure 5 , @ f sclk = 5.4mhz (1) 58 - - ns sclkrise sclk rise time see figure 5 , @ f sclk = 5.4mhz (1) - - 21 ns sclkfall sclk fall time see figure 5 , @ f sclk = 5.4mhz (1) - - 21 ns csrise channel select (cs) rise time see figure 5 (1) --100ns csfall channel select (cs) fall time see figure 5 (1) --100ns cslead channel select (cs) lead time see figure 6 (1) 455 - - ns cslag channel select (cs) lag time see figure 6 (1) 50 - - ns dirise input data (di) rise time see figure 5 , @ f sclk = 5.4mhz (1) - - 30 ns difall input data (di) fall time see figure 5 @ f sclk = 5.4mhz (1) - - 30 ns disus input data (di) set-up time see figure 6 , @ f sclk = 5.4mhz (1) 15 - - ns dihs input data (di) hold time see figure 6 , @ f sclk = 5.4mhz (1) 10 - - ns cs2sclk cs rise to sclk rise see figure 6 , @ f sclk = 5.4mhz (1) 40 - 300 ns 1. guaranteed by design.
l9733 electrical performance characteristics doc id 11319 rev 11 17/34 figure 3. do loading for disable time measurement figure 4. output loading for slew rate measurements figure 5. spi input/output timings figure 6. spi timing diagram 1 k ? vcc do 1 k ? +5 v 1.0 v 4.0 v 0 v dodis cs do 1 k ? vcc do 1 k ? +5 v 1.0 v 4.0 v 0 v dodis cs do vbat outputs 1-8 all low side outputs must meet the slew rate requirements of this load condition 180 ? outputs 1-8 all high side outputs must meet the slew rate requirements of this load condition 180 ? sclklm sclkhm sclkwid s clkfall sclkrise sclk csfall csrise difall dirise dofall dorise cs do di 10% 90% 10% 90% 90% 10% 10% 90% sclklm sclkhm sclkwid s clkfall sclkrise sclk csfall csrise difall dirise dofall dorise cs do di 10% 90% 10% 90% 90% 10% 10% 90% cs sclk do di cs lag do dis do a do hm do sum fault lsb fault msb di lsb di msb di cs lead di hs di sus cs2sclk cs sclk do di cs lag do dis do a do hm do sum fault lsb fault msb di lsb di msb di cs lead di hs di sus cs2sclk
functional description l9733 18/34 doc id 11319 rev 11 4 functional description l9733 integrates 8 self-configuring outputs (out1-8) which are able to drive either incandescent lamps, inductive loads (non-pwm'd, in pwm is necessary an external diode to reduce flyback power dissipation), or resistive loads biased to vbat (low-side configuration) or to gnd (high-side configuration). these outputs can be enabled and disabled via the spi bus. each of these outputs has a short circuit protection (with 0.8-2.4 amps threshold) selectable via spi bus between a filtered switching off overcurrent protection or a linear current limitation (default condition after power on is switching off protection enabled). an over-temperature protection as described in section 2.1 is available for each outputs. when a high-side configured output is commanded off after having been commanded on, the source voltage will go to (vgnd - 15 v). this is due to the design of the circuitry and the transconductance of the mosfet. when a low-side configured output is commanded off after having been commanded on , the output voltage will rise to the internal zener clamp voltage (50 vdc minimum) due to the flyback of the inductive load. outputs 1-8 are able to drive any combination of inductive loads or lamps at one time. inductive loads for the l9733 can range from 35mh to a maximum of 325 mh. the recommended worst-case solenoid loads (at -40 c) are calculated using a minimum resistance of 40 ? for each output. the maximum single pulse inductive load energy the l9733 outputs is able to be safely handle is 20 mj at -40 c to 125 c (worst-case load of 325 mh and 40 ? ). 4.1 configurations for outputs 1-8 the drain and source pins for each output must be connected in one of the two following configurations (see figure 7 ). 4.1.1 low-side drivers when any combination of outputs 1-8 are connected in a low-side drive configuration the source of the applicable output (src1-8) shall be connected to ground. the drain of the applicable output (drn1-8) shall be connected to the low-side of the load. 4.1.2 high-side drivers when any combination of outputs 1-8 are connected in a high-side drive configuration the drain of the applicable output (drn1-8) shall be connected to vbat. the source of the applicable output (src1-8) shall be connected to the high-side of the load. 4.2 outputs 1-5 these five outputs can be used as either high or low-side drives. the room temperature rdson of these outputs is 0.7 ? . a current limited (100 a max) voltage generator is connected to src 1-5 for open load and short to gnd detection when a low-side configured output is commanded off. another current limited (100 a max if vdrn 1-5 > 60 %vbat, 280 a max if vdrn 1-5 < 60 % vbat) voltage generator is connected to drn 1-5 for open load and short to v bat detection when a high-side configured output is commanded off. drain pins of outputs 1-5 (drn1-5) are connected to the drains of the n channel mosfet
l9733 functional description doc id 11319 rev 11 19/34 transistors. source pins of outputs 1-5 (src1-5) are connected to the sources of the n-channel mosfet transistors. 4.3 outputs 6-8 these three self-configuring outputs can be used to drive either high or low-side loads. in addition to being controlled by the spi bus these outputs can also be enabled and disabled via the in6 & in7& in8 inputs. the in6, in7 and in8 inputs are logically or'd with the spi commands to allow either the in6 & in7 & in8 inputs or the spi commands to activate these outputs. the use of the in6 & in7 & in8 pins for pwm control on these outputs should only be done with non-inductive loads if an external flyback diode is not present. the room temperature rdson of these four outputs is 0.7 ? . a current limited (100a max) voltage generator is connected to src 6-8 for open load and short to gnd detection when a low-side configured output is commanded off. another current limited (100a max if vdrn 6-8 > 60%vbat, 280 a max if vdrn 6-8 < 60 %vbat) voltage generator is connected to drn 6-8 for open load and short to vbat detection when a high-side configured output is commanded off. drain pins of outputs 6-8 (drn6-8) are connected to the drains of the n channel mosfet transistors. source pins of outputs 6-8 (src6-8) are connected to the sources of the n channel mosfet transistors. 4.4 drn1-8 susceptibility to negative voltage transients all outputs connected in the low-side configuration must have a ceramic chip capacitor of 0.01f to 0.1 f connected from drain to ground. this is needed to prevent potential problems with the device operation due to the presence of fast negative transient(s) on the drain(s) of the device. adequate de-coupling capacitors from the drain (vbat) to ground shall be provided for high-side configured outputs. 4.5 supply pins 4.5.1 main power input (vdd) an external +5.0 0.5 vdc supply provided from an external source is the primary power source to the l9733. this supply is used as the power source for all of its internal logic circuitry and other miscellaneous functions. 4.5.2 battery supply (vbat) this input is the supply for the on board charge pump. this input shall be connected directly to battery. if this input is not connected to the same supply, without additional voltage drops, of the drains of any high-side connected output s, then the rdson of th at given output will be higher than the specified maximum. 4.5.3 discrete inputs voltage supply (vdo) this pin is used to supply the discrete input stages of l9733 and must be connected to the same voltage used to supply the peripherals of the processor interfaced to l9733.
functional description l9733 20/34 doc id 11319 rev 11 4.6 discrete inputs 4.6.1 output 6-8 enable input (in6, ln7, ln8) this input allows output 6 (or output 7, or output 8) to be enabled via this external pin without the use of the spi. the spi command and the in6-7 input are logically or'd together. a logic "1" on this input (in6, ln7 or ln8) will enable this output no matter what the status of the spi command register. a logic "0" on th is input will disable this output if the spi command register is not commanding this output on. this pins (in6, ln7 or ln8) can be left "open" if the internal output device is being controlled only via the spi. this input has a nominal 100k ? resistor connected from th is pin to ground, which will pull this pin to ground if an open circuit condition occur. this input is ideally suited for non-inductive loads that are pulse width modulated (pwm'd). this allows pwm control without the use of the spi inputs. 4.6.2 reset input (res) when this input goes low it re sets all the internal registers and switches off all the output stages. this input has a nominal 100 k ? resistor connect ed from this pin to vdd, which will pull this pin to vdd if an open circuit condition occur.
l9733 serial peripheral interface (spi) doc id 11319 rev 11 21/34 5 serial peripheral interface (spi) the l9733 has a serial peripheral interface consisting of serial clock (sclk), data out (do), data in (di), and chip select (cs). all outputs will be co ntrolled via the spi. the input pins cs, sclk, and di, thanks to vdo pin, have level input voltages allowing proper operation from microcontrollers that are using 5.0 or 3.3 volts for their vdd supply. the design of the l9733 allows a "daisy-chaining" of multiple l9733's to further reduce the need for controller pins. 5.1 serial data output (do) this output pin is in a tri-state condition when cs is a logic '1'. when cs is a logic '0', this pin transmits 16 bits of data from the fault regi ster to the digital controller. after the first 16 bits of do fault data are transmitted (after a cs transition from a logic '1' to a logic '0'), then the do output sequentially transmits the digital data that was just received (16 sclk cycles earlier) on the di pin. the do output continues to transmit the 16 sclk delayed bit data from the di input until cs eventually transitions from a logic '0' to a logic '1'. do data changes state 10 nsec or later, after the falling edge of sclk. the lsb is the first bit of the byte transmitted on do and the msb is the last bit of the byte transmitted on do, once cs transitions from a logic '1' to a logic '0'. 5.2 serial data input (di) this input takes data from the digital controller while cs is low. the l9733 accepts an 16 bit byte to command the outputs on or off. the l9733 also serially wraps around the di input bits to the do output after the do output transmits its 16 fault flag bits. the lsb is the first bit of each byte received on di and the msb is the last bit of each byte received on di, once cs transitions from a logic '1' to a logic '0'. the last 4 bits (b15-b12) of the first 16 bit byte are used as key-word. the 4 bits (b11-b8) of the first 16 bits byte are used to select writing mode between out8-1 status and diagnosis operating mode . the di input has a nominal 100 k ? resistor connected from this pin to the vdo pin, which pulls this pin to vdo if an open circuit condition occurs. 5.3 chip select (cs) this is the chip select input pi n. on the falling edge of cs, th e do pin is released from tri- state mode. while cs is low, register data are shifted in and shifted out the di pin and do pin, respectively, on each subsequent sclk. on the rising edge of cs, the do pin is tri- stated and the fault register is "cleared" if a valid di byte has been received. a valid di byte is defined as such: ? a multiple of 16 bits was received. ? a valid key-word was received the fault data is not cleared unless all of th e 2 previous conditions have been met. the cs input has a nominal 100 k ? resistor connected from this pin to the vdo pin, which pulls this pin to vdo if an open circuit condition occurs.
serial peripheral interface (spi) l9733 22/34 doc id 11319 rev 11 5.4 serial clock (sclk) this is the clock signal input for synchronization of serial data transfer. di data is shifted into the di input on the rising edge of sclk an d do data changes on t he falling edge of sclk. the sclk input has a nominal 100k ? resistor connected from this pin to the vdo pin, which pulls this pin to vdo if an open circuit condition occurs. 5.5 initial input command register and fault register spi cycle after initial application of vdd to the l9733, the input command register and the fault register are "cleared" by the por circuitry and that means that the default condition for the output status is off, the default diagnostic mode is no latch and the switching off overcurrent protection is enable. during th e initial spi cycle, and all subs equent cycles, valid fault data will be clocked out of do (fault bits). 5.6 input command register an input byte (16 bits) is routed to the command register. the content of this command register is given in table 9. additional di da ta will continue to be wr apped around to the do pin. if cs should happen to go high before complete reception of the current byte, this just transmitted byte shall be ignored (invalid). table 9. bit command register definition key word writing mode: output output status msb lsb 1 0 1 0 1 1 0 0 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 key word writing mode: diag driver diag mode msb lsb 1 0 1 0 0 0 1 1 diag 8 diag 7 diag 6 diag 5 diag 4 diag 3 diag 2 diag 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 key word writing mode: protect driver overcurrent protection msb lsb 1 0 1 0 1 0 1 0 ilim 8 ilim 7 ilim 6 ilim 5 ilim 4 ilim 3 ilim 2 ilim 1 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
l9733 serial peripheral interface (spi) doc id 11319 rev 11 23/34 table 10. command register logic definition bit state status writing mode b0-b7 0 out1 - out8 are commanded off output b0-b7 1 out1 - out8 are commanded on output b0-b7 0 out1 - out8 diagnostic is no latch mode diag b0-b7 1 out1 - out8 diagnostic is latch mode diag b0-b7 0 out1 - out8 switching off overcurrent protection protection b0-b7 1 out1 - out8 linear overcurrent protection protection
other l9733 features l9733 24/34 doc id 11319 rev 11 6 other l9733 features 6.1 charge pump usage in order to provide low rdson values when connected in a high-side configuration, a charge pump to drive the internal gate voltage(s) above vbat is implemented. the charge pump used on the l9733 doesn't need external capacitor. the l9733 uses a common charge pump and oscillator for all th e 8 configurable output channe ls. the charge pump uses the vbat supply connected directly to the vb pin. the normal range of the vbat voltage is 10 to 18v18v. however, the l9733 is functional with vbat voltages as low as 4.5v dc with eventually a degradation of rdson. the frequency range of this charge pump is from 3.6 to 7.6 mhz. the frequency is above 1.8 mhz in order to be above the am radio band and below 8.0 mhz so that harmonics do not get within the fm radio band. 6.2 waveshaping both the turn on and the turn off slew rates on all outputs (out1-8) are limited to between 10 s and 100 s for both rise and fall times (10 to 90 %, and vice versa), to reduce conducted emc energy in the vehicle's wiring harness. the characteristics of the turn-on and turn-off voltage is linear, with no discontinuities, during the output driver state transition. 6.3 por register initialization when the l9733 wakes up, the vdd supply to the l9733 is allowed from 0 to 5 vdc in 0.3 to 3ms. the l9733 has a por circuit, which monitors the vdd voltage. when the vdd voltage reaches an internal threshold, and remains above this trip level for at least 5 to 20 s, the command and fault registers are "cleared". before vdd reaches this trip level, none of the eight outputs are allowed to momentarily glitch on. 6.4 thermal shutdown each of the eight outputs has independent thermal protection circuitry that disables each output driver once the local n-channel mosfet's device temperature reaches between +151 and +200 c. a filter is present to validate the thermal fault (5 s to 20 s). there is a 5 to 15 c hysteresis between the enable and disable temperature levels. the faulted channel will periodically turn off and on until the fault condition is cleared, the ambient temperature is decreased sufficiently or the out put is commanded off. if a thermal shutdown, of one or more output drivers, is active during the falling edge of the chip select (cs) signal all the bits of the fault register are "setted" to "1" (thermal shutdown is not latched and could be read only in the moment it is present). the thermal fault is cleared on the rising edge of chip select if a valid di byte was received. note: due to the design of the l9733 each output's thermal limit "may not" be truly independent to the extent that if one output is shorted, it may impact the operation of other outputs (due to lateral heating in the die).
l9733 fault operation doc id 11319 rev 11 25/34 7 fault operation the fault diagnostic capab ility consists of one internal 16 bi ts shift register and 2 bits are used for each output. the diagnostic information are: no fault present, overcurrent, open load and short circuit. for L9733XP all of the faults will be cleared on the rising edge of ch ip select if a valid di byte was received. for l9733cn the ovc register will be cleared after t he end of the diagno sis restart time tr es or by the input signal (in) in low state. the other faults will be cleared on the rising edge of chip select if a vali d di byte was received. if all the bits b0-b15 of the fault register have value '1' it means that a thermal fault, at least on one of the eight independent outputs, occurred. 7.1 low-side configured output fault operation the diagnostic circuitry verifies for the low- side configured output the following condition: normal operation, open load, short circuit to gnd and overcurrent (only if the switching off protection, selectable for each channel via spi bus, is active). the diagnostic circuitry operates in two different modes, selected for each channel by spi: no latch mode and latch mode. the fault priority is overcurrent and then open load or short circuit to gnd, this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to gnd faults that happen before that the register is cleared will be ignored. 7.1.1 no latch mode this diagnostic operating mode doesn't latch open load and short to gnd faults. 1. open load the diagnostic of open load is detected only in off condition sensing the drn1-8 output voltage. this fault is detected on the fa lling edge of the cs input if the power table 11. fault register definition out 8 out 7 out6 out5 out4 out3 out2 out1 msb lsb d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 12. fault logic definition d1 d0 fault status 0 0 no fault is present 0 1 open load 1 0 short circuit to gnd (low-side) or short circuit to vbat (high-side) 1 1 overcurrent
fault operation l9733 26/34 doc id 11319 rev 11 drain voltage is inside the voltage range limited by the two thresholds vth_vbat and vth_gnd . an internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. short circuit to gnd the diagnostic of short circuit to gnd is detected only in off condition sensing the drn1-8 output voltage. this fault is detected on the falling edge of the cs input if the power drain voltage is lower than the vth_gnd threshold. 3. overcurrent the diagnostic of overcurrent is detected only in on condition, if the switching off protection of the channel is enabled (default), sensing the current level of the output power transistor. if the output current has been above the short threshold iovc for the filtering time tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. there are three possib ilities to restart one output after the fault has occurred: ? automatically after a time tres ? on the rising edge of cs if two valid di byte has been received and first the output status in the command register is written with logic '0' and then with a logic ?1? in the following spi cycle ? on the rising edge (low to high transition) at the corresponding parallel input pin (only for outputs 6-8). ? if the switching off protection is not active the on phase overcurrent protection is a linear current limitation and no diagnosis is available. the use of the in6-8 pins for pwm control on the outputs 6-8 could generates bad diagnostic behavior when the falling edge of cs happens a short time after the falling edge of in6-8 during the power mos transient. software filtering may be needed to ignore fault signals during drn6-8 transient after falling edge of in6-8. 7.1.2 latch mode this diagnostic operating mode latches all faults when they happen. 1. open load the diagnostic of open load is detected only in off condition sensing the drn1-8 output voltage. this fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds vth_vbat and vth_gnd for the filtering time tfilt . an internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. short circuit to gnd the diagnostic of short circuit to gnd is detected only in off condition sensing the drn1-8 output voltage. this fault is detected if the power drain voltage is lower than the vth_gnd threshold for the filtering time tfilt. 3. overcurrent the diagnostic of overcurrent is detected only in on condition, if the switching off protection of the channel is enabled (default), sensing the current level of the output power transistor. if the output current has been above the short threshold iovc for the filtering time tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. if the switching off protection is not active the on
l9733 fault operation doc id 11319 rev 11 27/34 phase overcurrent protection is a linear current limitation and no diagnosis is available. there are three possib ilities to restart one output after the fault has occurred: ? automatically after a time tres ? on the rising edge of cs if two valid di byte has been received and first the output status in the command register is written with logic '0' and then with a logic ?1? in the following spi cycle ? on the rising edge (low to high transition) at the corresponding parallel input pin (only for outputs 6-8). if the power mos transient, after a switching-off command, is longer than tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed. 7.2 high-side configured output fault operation the diagnostic circuitry verifies for the high-side configured output the following condition: normal operation, open load, short circuit to vbat and overcurrent (only if the switching off protection, selectable for each channel via spi bus, is active). the diagnostic circuitry operates in two different modes, selected for each channel by spi: no latch mode and latch mode. the fault priority is overcurrent and then open load or short circuit to vb, this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to vbat faults that happen before that the register is cleared will be ignored. 7.2.1 no latch mode this diagnostic operating mode doesn't latch open load and short to vbat faults. 1. open load the diagnostic of open load is detected only in off condition sensing the src1-8 output voltage. this fault is detected on the fa lling edge of the cs input if the power drain voltage is inside the voltage range limited by the two thresholds vth_vbat and vth_gnd. an internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. short circuit to vb the diagnostic of short circuit to vbat is detected only in off condition sensing the src1-8 output voltage. this fault is detect ed on the falling edge of the cs input if the power drain voltage is higher than the vth_vbat threshold. 3. overcurrent the diagnostic of overcurrent is detected only in on condition, if the switching off protection of the channel is enabled (default), sensing the current level of the output power transistor. if the output current has been above the short threshold iovc for the filtering time tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. there are three possib ilities to restart one output after the fault has occurred: ? automatically after a time tres ? on the rising edge of cs if two valid di byte has been received and first the output status in the command register is written with logic '0' and then with a logic ?1? in the following spi cycle
fault operation l9733 28/34 doc id 11319 rev 11 ? on the rising edge (low to high transition) at the corresponding parallel input pin (only for outputs 6-8). ? if the switching off protection is not active the on phase overcurrent protection is a linear current limitation and no diagnosis is available. the use of the in6-8 pins for pwm control on the outputs 6-8 could generates bad diagnostic behavior when t he falling edge of cs happens a short time after the falling edge of in6-8 during the power mos transient. software filtering may be needed to ignore f ault signals during drn6-8 transi ent after falling edge of in6-8. 7.2.2 latch mode this diagnostic operating mode latches all faults when they happen. 1. open load the diagnostic of open load is detected only in off condition sensing the src1-8 output voltage. this fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds vth_vbat and vth_gnd for the filtering time tfilt . an internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected. 2. short circuit to vb the diagnostic of short circuit to vbat is detected only in off condition sensing the src1-8 output voltage. this fault is detected if the power drain voltage is higher than the vth_vbat threshold for the filtering time tfilt . 3. overcurrent the diagnostic of overcurrent is detected only in on condition, if the switching off protection of the channel is enabled (default), sensing the current level of the output power transistor. if the output current has been above the short threshold iovc for the filtering time tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register. there are thre e possibilities to restart one outp ut after the fault has occurred: ? automatically after a time tres ? on the rising edge of cs if two valid di byte has been received and first the output status in the command register is written with logic '0' and then with a logic ?1? in the following spi cycle ? on the rising edge (low to high transition) at the corresponding parallel input pin (only for outputs 6-8). if the switching off protection is not active the on phase overcurrent protection is a linear current limitation and no diagnosis is available. if the power mos transient, after a switching-off command, is longer than tdel filtering time, a bad diagnostic behavior happens and software filtering may be needed.
l9733 fault operation doc id 11319 rev 11 29/34 figure 7. l9733 application schematic figure 8. l9733 hvac applicative examples 8 high/low side driver v bat drn[x] src[x] drn[x] src[x] vdo sclk di do cs in6 in7 in8 to driver 6 to driver 7 to driver 8 gnd spi control logic registers res vbat cp vdd high side driver configuration low side driver configuration 8 high/low side driver v bat drn[x] src[x] drn[x] src[x] vdo sclk di do cs in6 in7 in8 to driver 6 to driver 7 to driver 8 gnd spi control logic registers res vbat cp vdd high side driver configuration low side driver configuration high side driver configuration low side driver configuration four flap motors become sequentially driven. unipolar stepper motor are selected by 4 high-side configured switches. if the decoupling diodes are inside the motor housing, only 8 wires are needed to drive this arrangement. sm sm sm sm vbatt stall sense l9733 spi control logic four flap motors become sequentially driven. unipolar stepper motor are selected by 4 high-side configured switches. if the decoupling diodes are inside the motor housing, only 8 wires are needed to drive this arrangement. sm sm sm sm vbatt stall sense l9733 spi control logic vbatt m m m m m m control lo gic spi l9733 4 channels configured to low- and 4 channels configured to high side build a quad half bridge. vbatt m m m m m m control lo gic spi l9733 vbatt m m m m m m control lo gic spi l9733 4 channels configured to low- and 4 channels configured to high side build a quad half bridge. this can drive 3 dc-motors sequantially.
fault operation l9733 30/34 doc id 11319 rev 11 figure 9. l9733 powertrain applicative examples vbatt tach-out (pwm) fuel pump relay (opt pwm) power latch relay canister purge relay (opt pwm) mil lamp water lamp coolant fan relay key-on relay control logic spi l9733 main relays and lamps driving sm control logic spi l9733 idle speed control vbatt starter relay a/c compressor relay air pump relay a/c fan relay idle speed stepper motor driving and auxiliary loads vbatt tach-out (pwm) fuel pump relay (opt pwm) power latch relay canister purge relay (opt pwm) mil lamp water lamp coolant fan relay key-on relay control logic spi l9733 main relays and lamps driving sm control logic spi l9733 idle speed control vbatt starter relay a/c compressor relay air pump relay a/c fan relay idle speed stepper motor driving and auxiliary loads
l9733 application circuit doc id 11319 rev 11 31/34 8 application circuit figure 10. optimized circuit layout to achieve proper emi/esd capability vdd 5v spi gnd control all output c = 47nf ceramic 47?100nf ceramic vbat drnx module connector central ground plane (blue coloured) 47?100nf ceramic voltage reg. positive iso - pulse protection r1= 10...22 (emi improvement) reverse polarity & neg. iso -pulse protection battery in 6 in 7 in 8 vdd res sclk di do cs vdo capacitor impedance frequency c1 vbat supplies the floating charge pump. filtering capacitor c1 is important to achieve a proper emi performance. impedance minimum should fit to the critical frequency range. a series resistor to vbat can improve furthermore emi performance. vdd on/off for low quiescent current
package information l9733 32/34 doc id 11319 rev 11 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 11. powersso28 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.15 2.45 0.084 0.0965 a2 2.15 2.35 0.084 0.0925 a1 0 0.10 0 0.004 b 0.18 0.36 0.007 0.014 c 0.23 0.32 0.009 0.012 d (1) 10.10 10.50 0.398 0.413 e (1) 7.4 7.6 0.291 0.299 e0.65 0.025 e3 8.45 0.033 f 2.3 0.090 g 0.10 0.004 g1 0.06 0.002 h 10.10 10.50 0.398 0.413 h 0.40 0.016 k5? (typ) l 0.60 1.0 0.023 0.039 m 4.3 0.169 n 10? (max) o 1.2 0.047 q 0.8 0.031 s 2.9 0.114 t3.65 0.144 u 1.0 0.039 x 4.2 4.8 0.165 0.189 y 6.6 7.2 0.259 0.283 (1) "d? and ?e" do not include mold flash or protrusions mold flash or protrusions shall not exceed 0.15 mm per side(0.006?) powersso-28 7633868 c (exposed pad)
l9733 revision history doc id 11319 rev 11 33/34 10 revision history table 13. document revision history date revision changes 13-apr-2005 1 initial release. 15-jun-2006 2 changed only look and feel. 08-aug-2006 3 modified table 9: bit command register definition on page 22 . 28-may-2007 4 changed the min. value of the cslead parameter on the ta bl e 8 . 17-jul-2007 5 updated ta bl e 6 and ta b l e 7 . added new figure 4 . changed the status from preliminary data to datasheet. 03-aug-2007 6 updated in ta bl e 4 the esd parameter. 12-jun-2008 7 added order codes in table 1: device summary . added ?cs2sclk? parameter in table 8: spi characteristics and timings . updated figure 6: spi timing diagram . 02-dec-2008 8 updated table 1: device summary on page 1 . removed all references to the so-28 package. updated section 2.1: operating range and section 2.2: absolute maximum ratings . added section 2.1.1: functio nal operative range , section 2.1.2: jump start conditions , section 2.1.3: operation at low battery condition and section 2.1.4: operation at load dump condition . added section 8: application circuit . added ?por th ? parameter in table 6: dc characteristics . 13-may-2009 9 updated table 1: device summary on page 1 . updated figure 11: powersso28 mechanical data and package dimensions . 27-jul-2010 10 updated table 1: device summary on page 1 . updated section 7: fault operation on page 25 . 19-sep-2013 11 updated disclaimer.
l9733 34/34 doc id 11319 rev 11 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L9733XP

	To Download L9733XP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .